(1) Field of the Invention
The present invention relates to semiconductor manufacturing and is more particularly directed to a split-gate flash memory cell having a PIP (Poly-Interpoly oxide-Poly) capacitor with high unit capacitance, and also to a method of forming the same.
(2) Description of the Related Art
With the ever-decreasing of feature sizes, including that of capacitor areas, in very large and ultra large integrated circuit technologies (VLSI and ULSI) of related art, the parameters that affect the capacitance of capacitors are requiring closer scrutiny in order to be able keep the unit capacitance values from being lowered further. That is, a solution must be found to meet the contradictory requirements for increasing the packing density of memory cells on the one hand, and increasing the storage capacity of the same, on the other. As is known in the art, the most important parameters involved in increasing the capacitance of a capacitor are the area of the capacitor, and the dielectric constant and the thickness of the insulator between the plates of the capacitor. It is shown later in the embodiments of the present invention that the low unit capacitance of a conventional split-gate flash memory cell can be increased by simultaneously forming a PIP capacitor together with the polysilicon (poly) gates of the cell where the floating gate poly is used as the bottom plate, the gate oxide as the inter-poly oxide, and the control gate poly as the top plate of the PIP capacitor.
It is common in related art to form capacitors, in addition to resistors, transistors and diodes, in integrated circuits of various types. Capacitors formed within analog integrated circuit fabrications typically assure proper operation of those analog integrated circuits. Capacitors formed within digital integrated circuits typically provide charge storage locations for individual bits of digital data stored with those digital integrated circuits.
A known type of capacitor that is typically, though not exclusively, formed with an integrated circuit is a double layer polysilicon capacitor. Double layer polysilicon capacitors are formed from two substantially planar conductive polysilicon electrodes separated by a dielectric layer. Double layer polysilicon capacitors provide several advantages when used within integrated circuits. For example, double layer polysilicon capacitors may easily be formed within several locations within an integrated circuit.
Such a double layer polysilicon capacitor is shown within a Field Effect Transistor (FET) in FIG. 1. Capacitor (20) is formed along with poly-gate (30) on the same substrate (10). Field oxide (15) defines active region (13) of substrate (10). Poly-gate (30), formed over the active region, comprises a patterned first polysilicon layer (50) separated from substrate (10) by an intervening layer of gate oxide (40). The first bottom plate, or electrode, of capacitor (20) is formed simultaneously from the same first polysilicon layer (50) of poly-gate (30) over the field oxide region (15), as shown in FIG. 1. A patterned insulator layer (60) is next formed over first electrode (50), and a second patterned polysilicon layer (70) over the insulator. Thus, the patterned second polysilicon layer (70) forms the second polysilicon electrode of the double layer polysilicon capacitor (20).
Use of double layer polysilicon capacitors in integrated circuits is common in prior art. Yoo, et al., of U.S. Pat. No. 5,866,451 discloses a method of making a mixed-mode capacitor suitable for either digital or analog circuits integrated with logic and memory in the same chip. A second layer polysilicon layer is patterned to form the top plate of a double layer capacitor in the same chip. In U.S. Pat. No. 5,631,188, Chang, et al., show a double layer polysilicon capacitor exhibiting low voltage coefficient and a method for forming the same. Pan of U.S. Pat. No. 5,858,832, on the other hand, teaches a method of forming within an integrated circuit a high areal capacitance planar capacitor. A split-gate flash EEPROM cell is disclosed by Ahn in U.S. Pat. No. 5,652,161.
In the present invention, a different double layer polysilicon capacitor in a split-gate flash memory cell is disclosed. When a double layer polysilicon capacitor is formed simultaneously with the forming of a split-gate flash memory cell, as described later in the embodiments of the present invention, if the poly-oxide between the floating gate and the control gate of the split-gate flash is used as the insulator between the first and second electrodes of the capacitor, then the unit capacitance of the capacitor becomes low due to the excessive thickness of the poly-oxide. It is disclosed later in the embodiments that with a judicious use of an additional masking step, a much thinner gate-oxide, in place of the thick poly-oxide, can be used, thereby achieving a Poly-Interpoly-Poly (PIP) capacitor with higher unit capacitance in a split-gate flash memory cell.
It is therefore, an object of this invention to provide a PIP (Poly-Interpoly-Poly) capacitor with high capacitance in a split-gate flash memory cell.
It is another object of the present invention to provide a method of forming a PIP capacitor with high capacitance in a split-gate flash memory cell.
It is still another object of this invention to provide a method of forming a PIP capacitor having its first and second electrodes simultaneously formed with the polysilicon floating and control gates, respectively, of a split-gate flash memory cell.
It is yet another object of the present invention to provide a method of using the thin gate oxide layer of a split-gate flash memory cell in place of the poly-oxide of the polysilicon layer as the insulating layer between the electrodes of a PIP capacitor, thus yielding a high unit capacitance and high storage capacity for the memory cell.
These objects are accomplished by providing a semiconductor substrate having a gate region and a capacitor region, and a first gate dielectric layer formed thereon; a first polysilicon layer forming the floating gate of said memory cell in said gate region, and the first electrode of said PIP capacitor in said capacitor region; a second polysilicon layer forming the control gate of said memory cell in said gate region, and the second electrode of said PIP capacitor in said capacitor region; a second gate dielectric layer and a poly-oxide layer between the floating gate and the control gate in said gate region; and a third gate dielectric layer as the insulator layer between said first electrode and said second electrode of said PIP capacitor.
The objects are further accomplished by providing a semiconductor substrate having a gate region and a capacitor region, and a first gate dielectric layer formed thereon; depositing a first polysilicon layer to form the floating gate of said memory cell in said gate region, and to form the first electrode of said PIP capacitor in said capacitor region; forming a poly-oxide layer over said first polysilicon layer; forming a second gate dielectric layer over said substrate including said gate region and said capacitor region; ion implanting said first polysilicon layer in said capacitor region to control dopant level in said first electrode of said PIP capacitor; performing an oxide dip to remove said second gate dielectric layer from said substrate; forming a third gate dielectric layer over said substrate including over said poly-oxide layer over said floating gate, and over said first electrode of said PIP capacitor; and depositing a second polysilicon layer to form the control gate of said memory cell in said gate region, and to form the second electrode of said PIP capacitor in said capacitor region on said substrate.